Nonvolatile memory devices such as the EPROM device are widely used as unit cells of integrated circuit memory devices. As illustrated by FIGS. 1a-1b, a unit cell EPROM device ("I") according to the prior art includes a semiconductor substrate 10 having a plurality of field oxide isolation regions 12 therein and a plurality of gate oxide insulating layers 14a on a surface thereof. Floating gate electrodes 16a of the EPROM memory cell are also provided on the gate oxide insulating layers 14a. In addition, an electrically insulating oxide/nitride/oxide (ONO) capping layer 20 is provided on the floating gate electrodes 16a. A polycide control gate electrode 24 is also provided on a row of floating gate electrodes 16a and acts as a word line of the memory device.
Referring now to FIGS. 2-7, a method of forming the prior art memory device of FIGS. 1a-1b will now be described. In FIGS. 2-7, the portions of the substrate 10 designated by reference numeral "A" represent memory cell array portions of the substrate 10 and the portions of the substrate 10 designated by reference numeral "B" represent peripheral circuit portions of the substrate 10. As illustrated by FIG. 2, the prior art method includes the step of forming a plurality of field oxide isolation regions 12 on the semiconductor substrate 10. The portions of the substrate 10 that are not covered by the field oxide isolation regions 12 may comprise active regions. A thermal oxidation step may then be performed to define first gate insulating layers 14a on the active regions. A blanket layer of polysilicon is then deposited as a first electrically conductive layer 16. Next, a first photoresist pattern 18a may be formed on the first electrically conductive layer 16.
Referring now to FIG. 3, the first electrically conductive layer 16 may then be dry-etched to define a floating gate electrode 16a, using the first photoresist pattern 18a as an etching mask. The first photoresist pattern 18a is then removed. Next, a blanket layer of an electrically insulating layer 20, which may comprise an oxide-nitride-oxide (ONO) composite insulating layer, is deposited. A blanket photoresist layer is then deposited on the electrically insulating layer 20. Conventional photolithography steps may then be performed to convert the blanket photoresist layer into a second photoresist pattern 18b on the memory cell array portion "A" of the substrate.
Referring now to FIG. 4, an etching step is then performed to remove the portion of the electrically insulating layer 20 extending opposite the peripheral circuit portion "B" of the substrate 10. During this etching step, a portion of the first gate insulating layer 14a on the peripheral circuit portion "B" of the substrate may also be etched somewhat. As illustrated best by FIG. 5, a wet etching step is then performed to remove the first gate insulating layer 14a from the peripheral circuit portion "B" of the substrate 10. This etching step is performed using the second photoresist pattern 18b as an etching mask. Next, a blanket layer 22 of an electrically conductive material (e.g., polycide) is then deposited on the substrate 10.
Referring now to FIG. 6, a third photoresist pattern 18c is then formed on the peripheral circuit portion "B" of the substrate 10 using conventional techniques. A dry etching step is then performed to convert the blanket layer 22 of second electrically conductive material into a plurality of control electrodes 24 (e.g., word lines) having the shapes illustrated by FIG. 1a. Referring now to FIG. 7, the third photoresist pattern 18c is removed and followed by the step of forming a fourth photoresist pattern 18d on the substrate 10. This fourth photoresist pattern 18d exposes the peripheral circuit portion "B" of the substrate 10. Another etching step (e.g., dry etching step) is then performed to convert a portion of the blanket layer 22 on the peripheral circuit portion "B" of the substrate 10 into a gate electrode 26. The fourth photoresist pattern 18d is then removed.
Unfortunately, the use of four masks in the method of FIGS. 2-7 can limit process yield and increase manufacturing costs. Thus, notwithstanding the above-described method, there continues to be a need for improved methods of forming integrated circuit memory devices.